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Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
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Size: 8192 |
Author: Jerd Hu |
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Description: a verilog code about dac of audio codec on fpga board.
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Size: 1024 |
Author: DCLAB |
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Description: FPGA的学习,熟悉QuartusII软件的各种功能,各种逻辑算法设计,接口模块(RS232,LCD,VGA,SPI,I2c等)的设计,时序分析,硬件优化等,自己开始设计简单的FPGA板子。
③、NiosII的学习,熟悉NiosII的开发流程,熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构,设计NiosII开发板,编写NiosII C语言程序,调试板子各模块功能。-Verilog语言的学习,熟悉Verilog语言的各种语法。
②、FPGA的学习,熟悉QuartusII软件的各种功能,各种逻辑算法设计,接口模块(RS232,LCD,VGA,SPI,I2c等)的设计,时序分析,硬件优化等,自己开始设计简单的FPGA板子。
③、NiosII的学习,熟悉NiosII的开发流程,熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构,设计NiosII开发板,编写NiosII C语言程序,调试板子各模块功能。
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Size: 22794240 |
Author: onejacky |
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Description: spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
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Size: 13312 |
Author: 张文 |
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Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件,传输模式和时钟相位均可以指定,采用同步时钟设计,可以工作在很高的频率下。支持主机及从机模式,强烈推荐使用!-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
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Size: 13312 |
Author: 中国 |
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Description: spi接口 verilog版本, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:-spi interface, verilog version, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:
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Size: 2624512 |
Author: shen |
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Description: 该文件是I2S 转 SPI的Verilog的源代码,可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into
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Size: 110592 |
Author: andy |
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Description: 串行flash的写及擦除操作,串行flash,spi接口,支持并口输出-Serial flash write and erase operations, serial flash, spi interface, support for parallel port output
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Size: 1024 |
Author: 王伯祥 |
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Description: 这是一个SPI串行总线接口的Verilog实现-It is a Verilog SPI serial bus interface implementation
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Size: 2048 |
Author: 王强 |
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Description: sd卡spi接口的verilog程序,quartus2,全部调好能已经应用于SD卡模块。-sd card spi interface verilog program, quartus2, all tuned to have been used in SD card module.
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Size: 2700288 |
Author: 洪传荣 |
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Description: DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog-DA-chip SPI protocol output control does not read write-only FPGA with verilog
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Size: 1024 |
Author: wuzhongpeng |
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Description: SPI IP核源码,包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code
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Size: 628736 |
Author: 任林枫 |
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Description: 对SPI协议的RTL实现,相当典型的一个例子。包括时钟分频,移位逻辑等等。-the verilog for spi
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Size: 598016 |
Author: 刘明 |
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Description: 这个文件的主要功能就是spi串行通行接口的verilog实现,程序描写很全面,还有一些注解。-This file is the main function verilog spi serial communication interface implementation, the program is fully described, and some comments.
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Size: 7168 |
Author: fuchao |
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Description: 一个简单的 SPI 的 verilog 程序 。 包含两个子模块。-A simple SPI' s verilog program. Contains two sub-modules.
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Size: 372736 |
Author: 王龙 |
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Description: 非常全面详细的SPI接口的verilog源代码-Very comprehensive and detailed source code verilog SPI interface
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Size: 4143104 |
Author: hechunzhi99 |
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Description: 含有fifo缓冲器的SPI接口源代码,用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
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Size: 49152 |
Author: hechunzhi99 |
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Description: SPI的Verilog实现(非常的全面和详细,还带有SPI算法的注解)-SPI in Verilog implementation (a very comprehensive and detailed, but also with the SPI algorithm annotation)
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Size: 7168 |
Author: Jane |
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Description: SPI Slave example (VERILOG HDL)
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Size: 1024 |
Author: igor |
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Description: SPI控制器,基于VERILOG描述,分模块设计,共6个模块,时钟产生模块,移位模块,主模块,从模块,定义模块,顶层模块。-SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.
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Size: 492544 |
Author: Liuhuan |
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